1. Field of Invention
The present invention relates to a half-bridge LLC resonant converter with self-driven synchronous rectifiers.
2. Related Art
FIG. 1 shows a circuit diagram of a prior art. An ideal transformer T0 includes a primary winding Np and two secondary windings Ns. A primary circuit is connected to the Np and a secondary circuit to the two Ns.
The primary circuit includes a first switch transistor M1, a second switch transistor M2 and an LLC resonant tank, which includes a magnetizing inductor Lm, a resonant inductor Lr and a resonant capacitor Cr. M1 and M2 are connected between an input voltage source Vin and a primary ground terminal in a half-bridge configuration, where the point at which M1, M2 and the LLC resonant tank intersect is called a first node P, and the LLC resonant tank is connected between the first node P and the primary ground terminal.
It is emphatically noted that a practical transformer T1 is equivalent to the integration of the ideal transformer T0 including the Np and the two Ns, Lm and a leakage inductor, where Lm is in parallel with the Np, and the leakage inductor is in series with the parallel circuit of Lm and Np. Lm can be measured from the primary side with the two Ns open-circuited, and the leakage inductance can be measured from the primary side with the two Ns short-circuited. If the Np and the two Ns of T1 are wound with a sandwich structure, then an external Lr is necessary, but if the Np and the two Ns of T1 are wound on a slotted bobbin, then the Lr can be provided by the leakage inductance of T1. A transformer with a slotted bobbin is used in this example.
The secondary circuit includes a first rectifier diode D1, a second rectifier diode D2 and an output capacitor Co. D1 and D2 are connected in a center-tapped common-cathode rectifier configuration between the two Ns and Co, where the two Ns are connected in a center-tapped configuration at the secondary ground terminal, and D1 and D2 are connected in a common-cathode rectifier configuration at the output voltage terminal with an output voltage Vo.
For the convenience of illustration, the circuit parameters are defined as follows: fs is the switching frequency of M1 and M2,
      f    r    =      1          2      ⁢      π      ⁢                                    L            r                    ⁢                      C            r                              is the resonant frequency of Lr and Cr,
  n  =            N      p              N      s      is the primary-to-secondary turns ratio of T0, Vo is the output voltage, and Vor=nVo is the reflected output voltage. Regarding the circuit variables, the reference polarities of the gate-source voltages vGSM1(t) and vGSM2(t) of M1 and M2, the resonant capacitor voltage vCr(t), the primary voltage vp(t) and the secondary voltage vs(t) as well as the reference directions of the resonant inductor current iLr(t), the magnetizing inductor current iLm(t), the primary current ip(t) and the secondary current is(t) are also shown in FIG. 1.
According to the conditions of fs<fr, fs=fr and fs>fr, the waveforms of vGSM1(t), vGSM2(t), iLr(t), iLm(t) and is(t) are shown in FIGS. 2a, 2b and 2c respectively. As shown in the figures, the waveforms of the first half period and the second half period are symmetrical, so only equivalent circuits and critical waveforms of the first half period are described and those of the second half period can be analogized using the symmetry.
Firstly, the physical meanings of t=t0, t=t1, t=tr and t=ts are interpreted as follows: t=t0 is the time when a resonant period resumes, t=t1 is the time when iLr(t) crosses 0, t=tr is the time when is(t) descends to 0 and t=ts is the time when vGSM1(t) switches to 0.
Regardless of fs≦fr or fs>fr, during the interval of t0≦t≦t1, vGSM1(t)=0, vGSM2(t)=0, iLr(t)<0 and iLr>iLm(t). M1 and M2 are turned off, iLr(t) flows through the body diode of M1, ip(t)=iLr(t)−iLm(t)>0 flows into the dotted terminal of Np, is(t)=nip>0 flows out of the dotted terminal of Ns, D1 is turned on and D2 is turned off. Lm does not participate in the resonance of Lr and Cr due to the clamp of Vor, iLr(t) and is(t) are quasi-sinusoidal waves and the rising slope of iLm(t) is equal to
            V      or              L      m        .D1 switches to on state at t=t0 under zero-current-switching (ZCS), and M1 switches to on state during t0≦t≦t1 under zero-voltage-switching (ZVS) and, more particularly, at t=t1 under ZVS and ZCS, so the switching losses are reduced.
Under the condition of fs≦fr (i.e. tr≦ts), is(t) descends to 0 before M1 turns off. The interval of t1≦t≦ts is divided into two subintervals t1≦t≦tr and tr≦t≦ts. During the subinterval of t1≦t≦tr, vGSM1(t)=Vcc, VGSM2(t)=0, iLr(t)>0 and iLr>iLm(t). M1 is turned on, M2 is turned off, iLr(t) flows through the channel of M1, ip(t)>0 flows into the dotted terminal of Np, is(t)>0 flows out of the dotted terminal of Ns, D1 is turned on and D2 is turned off. Lm does not participate in the resonance of Lr and Cr due to the clamp of Vor, iLr(t) and is(t) are quasi-sinusoidal waves and the rising slope of iLm(t) is equal to
            V      or              L      m        .D1 switches to off state at t=tr under ZCS. During the subinterval of tr≦t≦ts, vGSM1(t)=Vcc, vGSM2(t)=0, iLr(t)>0 and iLr=iLm(t). M1 is turned on, M2 is turned off, iLr(t) flows through the channel of M1, ip(t)=0, is(t)=0, both D1 and D2 are turned off. Lm participates the resonance of Lr and Cr, and the rising slope of iLr(t) and iLm(t) is smaller than
            V      or              L      m        .Especially,
                                          ⅆ                                          i                                  L                  m                                            ⁡                              (                t                )                                                          ⅆ            t                          <                              V            or                                L            m                              ⇒                        v          s                ⁡                  (          t          )                      =                                        L            m                    n                ⁢                              ⅆ                                          i                                  L                  m                                            ⁡                              (                t                )                                                          ⅆ            t                              <              V        o              ,D1 is reverse-biased by the voltage difference between Vo and vs(t) to turn off, and D2 switches to on state at t=ts under ZCS.
Under the condition of fs>fr (i.e. tr>ts), is(t) descends to 0 after M1 turns off. The interval t1≦t≦tr is divided into t1≦t≦ts and ts≦t≦tr. During t1≦t≦ts, vGSM1(t)=Vcc, vGSM2(t)=0, iLr(t)>0 and iLr(t)>iLm(t). M1 is turned on, M2 is turned off, iLr(t) flows through the channel of M1, ip(t) flows into the dotted terminal of Np, is(t) flows out of the dotted terminal of Ns, D1 is turned on and D2 is turned off. Lm does not participate in the resonance of Lr and Cr due to the clamp of Vor, iLr(t) and is(t) are quasi-sinusoidal waves and the rising slope of iLm(t) is equal to
            V      or              L      m        .During ts≦t≦tr, vGSM1(t)=0, vGSM2(t)=0, iLr(t)>0 and iLr>iLm(t). Both M1 and M2 are turned off, iLr(t) flows through the body diode of M2, ip(t) flows into the dotted terminal of Np, is(t) flows out of the dotted terminal of Ns, D1 is truned on and D2 is turned off. Lm does not participate in the resonance of Lr and Cr due to the clamp of Vor, iLr(t) and is(t) are quasi-sinusoidal waves and the rising slope of iLm(t) is equal to Vor/Lm. Especially,
                    ⅆ                              i                          L              m                                ⁡                      (            t            )                                      ⅆ        t              =                                        V            or                                L            m                          ⇒                              v            s                    ⁡                      (            t            )                              =                                                  L              m                        n                    ⁢                                    ⅆ                                                i                                      L                    m                                                  ⁡                                  (                  t                  )                                                                    ⅆ              t                                      =                  V          o                      ,D1 remains on. is(t=tr) commutates from D1 to D2 at t=tr under ZCS.
This conventional converter benefits from lower switching losses due to ZVS and ZCS but suffers from higher conduction losses due to the diode rectifiers. To reduce the conduction losses, self-driven synchronous rectifiers (SRs) are proposed. The primary switch transistors and the secondary SRs are driven by an IC controller and a gate driver simultaneously. Conceptually, the IC controller can be a primary IC controller or a secondary IC controller. Practically, a primary IC controller has three advantages over a secondary IC controller: (1) easier to buy from the market, (2) easier to cooperate with a primary power factor corrector and (3) easier to realize the protection functions of the converter. Based on a primary IC controller, a cost-effective half-bridge LLC resonant converter with self-driven synchronous rectifiers is proposed.